1+ day, 2+ hour ago  (195+ words) How a connected design methodology helps engineering teams accelerate development while maintaining consistency across the So C lifecycle. The post Automate the Pain Away: HW/SW Interface Design Methodology appeared first on Semiconductor Engineering. As System-on-Chip (So C) designs become increasingly…...

2+ week, 2+ day ago  (211+ words) A roadmap for operationalizing AI at scale and achieving sustained competitive advantage across the semiconductor lifecycle. The post 2026 ASMC " Building the Core Pillars for AI in Semiconductors appeared first on Semiconductor Engineering. Abstract: This presentation outlines a practical pathway for…...

3+ mon, 2+ week ago  (419+ words) Integrating a wireless chip and a microcontroller reduces complexity and improves power management. The goal isn't just integration. It's better outcomes. Integrating processing and connectivity helps reduce system complexity, improve reliability, strengthen security, and simplify the development experience for design…...

4+ mon, 2+ hour ago  (64+ words) Practical strategies, common pitfalls, and solutions to create efficient and reliable designs. The post 40 PCB Design Tips Every Designer Should Know: e Book appeared first on Semiconductor Engineering. This e Book details 40 essential PCB design tips, organized by 5 sections: Project…...

4+ mon, 2+ hour ago  (124+ words) How connected design data management can eliminate bottlenecks, accelerate innovation, and help organizations stay competitive in the rapidly evolving semiconductor landscape. The post Purpose-Built Tools for Connected Design appeared first on Semiconductor Engineering. Modern semiconductor design is a massive, data-driven…...

7+ mon, 2+ hour ago  (266+ words) Bringing logic, memory, and accelerators into tight physical proximity. Vertical stacking takes integration further by physically aligning these dies in three dimensions. Memory or accelerators can be placed directly above compute tiles, dramatically reducing interconnect distances. The result is higher…...

7+ mon, 5+ day ago  (1577+ words) Thin films for insulating different components are causing dissipation issues in advanced chips. Logic in AI server chips routinely operates at multi-kilowatt power levels, and the heat they generate must pass through a labyrinth of dielectrics, metal barriers, and interfaces…...

8+ mon, 2+ week ago  (391+ words) A new technical paper titled "The Impact of Process Variations on the Thermo-Mechanical Behavior of 3 D Integrated Circuits" was published by researchers at National Taiwan University and Lamar University. Abstract "The use of vertically stacked architectures in three-dimensional integrated circuits…...

8+ mon, 2+ week ago  (416+ words) Stacking dies will dramatically improve performance, but it's still a work in progress. SE: How different will chip design be with 3 D-ICs versus 2. 5 D and planar So Cs? Mueth: Yes, and if you have 10 interdependencies, now you've got to deal…...

9+ mon, 2+ hour ago  (552+ words) As more companies and startups join forces with government and academia in chip design projects, issues around data sharing, IP protection, and PDK access must be solved. However, there are several key challenges to group design projects, which are further…...